Amrita EEE × IIT Madras DS · Building at the seam

Intelligent systems,
end to end.

From world models to the silicon that runs them — RTL, verification, edge AI, and the agents that tie them together. I care about the engineering that turns intelligent models into real systems.

Open to AI systems · Edge AI · EDA roles

374.5 GOP/s patent-pending BNN accelerator

sub-100 ms ViT on AMD Versal · ISRO

SIH '25 finalist · IEEE GRSS & MunichTech winner

AGENTIC AI / LLMs / EDA / VERIFICATION / RL / EDGE AI / SILICON / DEVOPS / QUANTUM / AGENTIC AI / LLMs / EDA / VERIFICATION / RL / EDGE AI / SILICON / DEVOPS / QUANTUM /

logic [63:0] weights;

assign popcount = ...

always_ff @(posedge clk)

agent.run(tool)

memory.retrieve()

coverage += bins_hit;

quantize(INT8)

attention()

The systems I like to build

Nine domains. One stack.

Agentic AI

Planning, tool use, memory, and multi-agent workflows — systems that reason, act, and adapt.

planner→tool·memory→critic

Verification

UVM, cocotb, coverage, and adversarial testing — verification that goes beyond simply turning tests green.

stimulus→DUT→scoreboard→coverage

Silicon / RTL

SystemVerilog, systolic accelerators, and RTL — a patent-pending BNN array, down to tapeout literacy.

RTL→PE array→SRAM→accelerator

Edge AI

Hardware-aware vision transformers, quantization, and deployment — sub-100 ms inference on AMD Versal at ISRO.

FP32→INT8→NPU→inference

EDA

EDA automation, design flows, and intelligent tooling — pushing hardware development toward autonomous workflows.

RTL→synthesis→P&R→timing

LLMs

On-device inference, quantization, and RAG — making large models fit where they actually have to run.

Reinforcement Learning

Model-based RL and world models — planning inside a learned latent instead of the real world.

DevOps

Docker, CI/CD, APIs, and deployment — turning research prototypes into reproducible systems.

Quantumexploring

Variational circuits and QML — the newest thread, learning in the open.

Selected work

Things I've actually built.

01 — FLAGSHIP

Agentic RISC-V Verification Platform

VerificationAgentic AIRISC-Vcocotb · UVM

Twelve agents that generate a testbench, run the design against a golden ISS, diff the two commit logs instruction by instruction, analyse coverage, and write new tests aimed at what the campaign hasn't reached. Underneath sits VOE — a frozen kernel where a “verified” claim can't exist without a re-checkable witness, every policy pre-registered in an append-only ledger.

View case study →

12 agents

most run with no EDA toolchain

the green result
that means nothing — solved

02 — RESEARCH

BNN Systolic Accelerator

SiliconSystemVerilogEdge AI

A patent-pending 64×64 systolic-array binary neural network accelerator, designed and verified in RTL for energy-efficient edge inference.

View case study →

374.5 GOP/s

92.8 GOP/s/W · 10.67× speedup

03 — AGENT

Anvil — LLM Quantization Agent

LLMsEdge AIArm KleidiAI

Searches 2.7×10⁸ per-layer quant configs with a surrogate-guided planner; matched greedy's 60-evaluation result in ~9 on-device evals. Built for the Arm AI Optimization Challenge.

View case study →

1.8× faster

time-to-first-token · better perplexity

Where I've worked

Internships & research.

May – Jun 2026
Hyderabad

ISRO

Edge AI Research Intern

ADRIN — NRSC, ISRO

Deployed an INT8-quantized MobileViTv2-XS vision transformer on the AMD Versal VCK190 (Vitis AI / HLS / Vivado) for onboard Earth-observation inference; ran latency/throughput/utilization trade-offs across Versal and Zynq.

sub-100 ms onboard inference

Jul 2025 – Feb 2026
Coimbatore

BNN

Hardware Research Engineer

BNN Systolic Accelerator · Research

Designed and verified a patent-pending 64×64 systolic-array binary neural network accelerator in SystemVerilog for energy-efficient edge inference, with full RTL verification and performance analysis.

374.5 GOP/s · 92.8 GOP/s/W · 10.67× speedup

May – Jul 2025
Bengaluru

WIP

AI-ML Engineering Intern

Wipro

Built a production spam/ham text classifier (TF-IDF → Random Forest with a logistic-regression meta-classifier) for high-volume enterprise streams, then re-architected the real-time inference pipeline with batching and vectorized preprocessing.

−13.4% processing latency at scale

Recognition