02 — RESEARCH · 2025 – 2026
BNN Systolic Accelerator
374.5 GOP/s
92.8 GOP/s/W · 10.67× speedup
SystemVerilog · RTL verification · systolic array
The problem
Energy-efficient edge AI inference is a hardware problem, not just a quantized-model problem. A binary neural network turns a multiply-accumulate into XNOR + popcount — which is a sentence about silicon, not about machine learning.
The design
A 64×64 systolic-array accelerator in SystemVerilog, with full RTL verification and performance analysis. The array streams binarized weights and activations through processing elements built around XNOR + popcount.
The result
374.5 GOP/s, 92.8 GOP/s/W, a 10.67× speedup over the baseline — and a patent-pending architecture for energy-efficient edge inference.
Code private / patent-pendingAll work